Silicon implementation of an artificial dendritic tree

The silicon implementation of an artificial passive dendritic tree which can be used to process and classify dynamic signals is described. The electrical circuit architecture is modeled after complex neurons in the vertebrate brain which have spatially extensive dendritic tree structures that support large numbers of synapses. The circuit is primarily analog and, as in the biological model system, is virtually immune to process variations and other factors which often plague more conventional circuits. The nonlinear circuit is sensitive to both temporal and spatial signal characteristics but does not make use of the conventional neural network concept of weights, and as such does not use multipliers, adders, or other complex computational devices. As in biological neuronal circuits, a high degree of local connectivity is required. However, unlike biology, multiplexing of connections is done to reduce the number of conductors to a reasonable level for standard packages.<>