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引用次数: 127
摘要
提出了一种适用于智能存储器可重构结构的高效低摆幅互连方案。通过使用单独的电源、全局时钟和差分信号，我们降低了设计的复杂性;通过使用超速驱动电路、均衡技术和传感器放大器，我们保持了高性能。采用1.8 V 0.18-/spl mu/m技术的测试芯片，在1ghz下，10mm总线的功耗<1pJ/bit，与全摆幅信号相比，功耗节省高达10倍，并且放大器输入偏置电压低于100 mV。
We present circuits for a high-efficiency low-swing interconnect scheme suitable for the Smart Memories reconfigurable architecture. By using a separate supply, global clocking, and differential signaling, we reduce design complexity; and by using overdrive circuits, equalization techniques, and sense-amplifiers we retain high performance. A testchip built in a 1.8 V 0.18-/spl mu/m technology consumed <1pJ/bit for a 10 mm bus at 1 GHz, a power savings over full-swing signaling of up to 10 x, and demonstrated amplifier input offset voltages of under 100 mV.
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