微处理器核心

Proceedings IEEE European Test Workshop Pub Date : 1900-01-01 DOI:10.1109/ETW.2000.873774

A. Burdass, G. Campbell, R. Grisenthwaite, D. Gwilt, P. Harrod, R. York

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引用次数: 3

摘要

本文比较和对比了两种非常不同的方法来测试缓存的CPU宏单元，它们通常嵌入在片上系统(SoC)中。一个使用测试总线来应用功能向量，而另一个使用扫描插入，内存BIST和测试项圈的组合。还讨论了IP保护问题和非侵入式跟踪。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Microprocessor cores

This paper compares and contrast two very different approaches to testing cached CPU macrocells that are typically embedded in a System on Chip (SoC). One uses a test bus to apply functional vectors, while the other uses a combination of scan insertion, memory BIST and test collars. IP protection issues and nonintrusive tracing are also discussed.

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Proceedings IEEE European Test Workshop

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