25纳米薄边壁间隔层原子层沉积，增强FinFET性能

2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 2011-10-13 DOI:10.1109/ESSDERC.2011.6044229

K. Endo, Y. Ishikawa, T. Matsukawa, Yongxum Liu, S. Oruchi, K. Sakamoto, J. Tsukada, H. Yamauchi, M. Masahara

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引用次数: 2

摘要

我们利用SiO2薄膜的原子层沉积作为栅极的侧壁间隔，成功地制造了源极/漏极长度为25nm的finfet。通过降低寄生电阻，成功地提高了FinFET的性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Atomic layer deposition of 25-nm-thin sidewall spacer for enhancement of FinFET performance

We have successfully fabricated FinFETs with a 25-nm-short extension of the source/drain by using atomic layer deposition of SiO2 thin films for the side-wall spacer of the gate electrode. The performance of the FinFET has been successfully improved by the reduction of the parasitic resistance.

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2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)

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