Sola Woo, Gihun Choe, A. Khan, S. Datta, Shimeng Yu
{"title":"用于多电平单元3D NAND闪存的铁电-金属场效应晶体管设计","authors":"Sola Woo, Gihun Choe, A. Khan, S. Datta, Shimeng Yu","doi":"10.1109/IMW56887.2023.10145961","DOIUrl":null,"url":null,"abstract":"Ferroelectric-metal field-effect transistor (FeMFET) based three-dimensional NAND architecture (3D NAND) is investigated for multi-level cell (MLC) operation. The FeMFET with a gate-stack of metal-ferroelectric-metal-insulatorsemiconductor (MFMIS) is used for improving memory window to $1.60\\mathrm{~V}$ and alleviating variability caused by ferroelectric phase variation for MLC operation. In addition, the read-out current is examined by increasing the vertical gate-stack from 256-layer to 512-layer using page buffer circuit for sensing operation. Leveraging TCAD modeling and SPICE simulation, we demonstrate that FeMFET-based 3D NAND can operate 512-layer with sufficient sense margin for MLC operation.","PeriodicalId":153429,"journal":{"name":"2023 IEEE International Memory Workshop (IMW)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of Ferroelectric-Metal Field-Effect Transistor for Multi-Level-Cell 3D NAND Flash\",\"authors\":\"Sola Woo, Gihun Choe, A. Khan, S. Datta, Shimeng Yu\",\"doi\":\"10.1109/IMW56887.2023.10145961\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Ferroelectric-metal field-effect transistor (FeMFET) based three-dimensional NAND architecture (3D NAND) is investigated for multi-level cell (MLC) operation. The FeMFET with a gate-stack of metal-ferroelectric-metal-insulatorsemiconductor (MFMIS) is used for improving memory window to $1.60\\\\mathrm{~V}$ and alleviating variability caused by ferroelectric phase variation for MLC operation. In addition, the read-out current is examined by increasing the vertical gate-stack from 256-layer to 512-layer using page buffer circuit for sensing operation. Leveraging TCAD modeling and SPICE simulation, we demonstrate that FeMFET-based 3D NAND can operate 512-layer with sufficient sense margin for MLC operation.\",\"PeriodicalId\":153429,\"journal\":{\"name\":\"2023 IEEE International Memory Workshop (IMW)\",\"volume\":\"79 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2023 IEEE International Memory Workshop (IMW)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IMW56887.2023.10145961\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 IEEE International Memory Workshop (IMW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMW56887.2023.10145961","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of Ferroelectric-Metal Field-Effect Transistor for Multi-Level-Cell 3D NAND Flash
Ferroelectric-metal field-effect transistor (FeMFET) based three-dimensional NAND architecture (3D NAND) is investigated for multi-level cell (MLC) operation. The FeMFET with a gate-stack of metal-ferroelectric-metal-insulatorsemiconductor (MFMIS) is used for improving memory window to $1.60\mathrm{~V}$ and alleviating variability caused by ferroelectric phase variation for MLC operation. In addition, the read-out current is examined by increasing the vertical gate-stack from 256-layer to 512-layer using page buffer circuit for sensing operation. Leveraging TCAD modeling and SPICE simulation, we demonstrate that FeMFET-based 3D NAND can operate 512-layer with sufficient sense margin for MLC operation.
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