采用薄栅氧化膜晶体管的嵌入式DRAM宏保持时间长

Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434) Pub Date : 2000-08-28 DOI:10.1109/APASIC.2000.896981

R. Fukuda, S. Miyano, T. Namekawa, R. Haga, O. Wada, S. Takeda, K. Numata, M. Habu, H. Koike, H. Takato

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摘要

本文介绍了采用负字线(WL)结构的薄栅氧化晶体管在嵌入式DRAM宏中的优点。构造了负WL结构的宏和常规WL结构的宏。我们发现负WL结构的保留时间比传统WL结构长5倍以上。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Long retention time of embedded DRAM macro with thin gate oxide film transistors

This paper describes the advantages of the thin gate oxide transistors with negative word-line (WL) architecture implemented in the embedded DRAM macro. The macros with the negative WL architecture are fabricated as well as the macros with the conventional WL architecture. We found the retention time of the negative WL architecture is longer by more than 5 times than that of the conventional WL architecture.

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Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)

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