H. Shin, Sangkyung Won, Do-Hee Kim, Byung-Soon Choi, G.H. Kim, Myeonghee Oh, Jaeseung Choi, J. Kye
{"title":"基于28nm的32Mb嵌入式闪存，具有最佳电池效率和稳健的设计成就，在0.85V下具有13.48Mb/mm2的性能","authors":"H. Shin, Sangkyung Won, Do-Hee Kim, Byung-Soon Choi, G.H. Kim, Myeonghee Oh, Jaeseung Choi, J. Kye","doi":"10.1109/vlsitechnologyandcir46769.2022.9830151","DOIUrl":null,"url":null,"abstract":"A 28nm embedded Flash memory presented in this paper maximizes memory operation efficiently while implementing an optimal size. The peripheral size was reduced by applying the temperature auto tracking assist circuit with Bidirectional and Series-Parallel Conversion (BSPC) charge pump technology, and the IP size was improved by implementing the maximum density per mat by enhancing the sensing margin using Source Line Floating (SLF) technology. Also, using Program Current Auto Control (PCAC) scheme, program operation efficiency was improved and characteristic deviation of bit cell was reduced. With the application of these technologies, 72 bits program and 144 bits read operation are supported, and chip size 2.367mm2 is implemented based on 32Mbit density. This has the best competitiveness considering the area Mbit (13.48Mb/mm2) and Cell efficiency (68.1%).","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 32Mb Embedded Flash Memory based on 28nm with the best Cell Efficiency and Robust Design achievement featuring 13.48Mb/mm2 at 0.85V\",\"authors\":\"H. Shin, Sangkyung Won, Do-Hee Kim, Byung-Soon Choi, G.H. Kim, Myeonghee Oh, Jaeseung Choi, J. Kye\",\"doi\":\"10.1109/vlsitechnologyandcir46769.2022.9830151\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 28nm embedded Flash memory presented in this paper maximizes memory operation efficiently while implementing an optimal size. The peripheral size was reduced by applying the temperature auto tracking assist circuit with Bidirectional and Series-Parallel Conversion (BSPC) charge pump technology, and the IP size was improved by implementing the maximum density per mat by enhancing the sensing margin using Source Line Floating (SLF) technology. Also, using Program Current Auto Control (PCAC) scheme, program operation efficiency was improved and characteristic deviation of bit cell was reduced. With the application of these technologies, 72 bits program and 144 bits read operation are supported, and chip size 2.367mm2 is implemented based on 32Mbit density. This has the best competitiveness considering the area Mbit (13.48Mb/mm2) and Cell efficiency (68.1%).\",\"PeriodicalId\":332454,\"journal\":{\"name\":\"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830151\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830151","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 32Mb Embedded Flash Memory based on 28nm with the best Cell Efficiency and Robust Design achievement featuring 13.48Mb/mm2 at 0.85V
A 28nm embedded Flash memory presented in this paper maximizes memory operation efficiently while implementing an optimal size. The peripheral size was reduced by applying the temperature auto tracking assist circuit with Bidirectional and Series-Parallel Conversion (BSPC) charge pump technology, and the IP size was improved by implementing the maximum density per mat by enhancing the sensing margin using Source Line Floating (SLF) technology. Also, using Program Current Auto Control (PCAC) scheme, program operation efficiency was improved and characteristic deviation of bit cell was reduced. With the application of these technologies, 72 bits program and 144 bits read operation are supported, and chip size 2.367mm2 is implemented based on 32Mbit density. This has the best competitiveness considering the area Mbit (13.48Mb/mm2) and Cell efficiency (68.1%).
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
