{"title":"一个60 db DR PGA与直流偏置校准短距离无线接收机","authors":"Xiaokun Zhao, Zheng Song, B. Chi","doi":"10.1109/VLSI-DAT.2015.7114572","DOIUrl":null,"url":null,"abstract":"A low-power, high-linearity programmable gain amplifier (PGA) with DC-offset calibration (DCOC) is presented. The PGA has a large gain range from 5dB to 65dB with 1dB step. Benefited from an improved source-degenerated architecture, the measured gain error is less than 0.15dB. By adopting the closed-loop architecture and resistor array optimization, the PGA achieves an OIP3 of 19.2dBm and an output P1dB of 7.58dBm. Two methods are implemented for DC-offset cancellation: RC high-pass filter (HPF) and digital-assisted DCOC. Implemented in TSMC 0.18um process, the PGA occupies 0.37mm2 die area and consumes 1.82mA (I and Q path) from a 1.7V supply.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A 60-dB DR PGA with DC-offset calibration for short-distance wireless receiver\",\"authors\":\"Xiaokun Zhao, Zheng Song, B. Chi\",\"doi\":\"10.1109/VLSI-DAT.2015.7114572\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A low-power, high-linearity programmable gain amplifier (PGA) with DC-offset calibration (DCOC) is presented. The PGA has a large gain range from 5dB to 65dB with 1dB step. Benefited from an improved source-degenerated architecture, the measured gain error is less than 0.15dB. By adopting the closed-loop architecture and resistor array optimization, the PGA achieves an OIP3 of 19.2dBm and an output P1dB of 7.58dBm. Two methods are implemented for DC-offset cancellation: RC high-pass filter (HPF) and digital-assisted DCOC. Implemented in TSMC 0.18um process, the PGA occupies 0.37mm2 die area and consumes 1.82mA (I and Q path) from a 1.7V supply.\",\"PeriodicalId\":369130,\"journal\":{\"name\":\"VLSI Design, Automation and Test(VLSI-DAT)\",\"volume\":\"14 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-04-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"VLSI Design, Automation and Test(VLSI-DAT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSI-DAT.2015.7114572\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"VLSI Design, Automation and Test(VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-DAT.2015.7114572","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 60-dB DR PGA with DC-offset calibration for short-distance wireless receiver
A low-power, high-linearity programmable gain amplifier (PGA) with DC-offset calibration (DCOC) is presented. The PGA has a large gain range from 5dB to 65dB with 1dB step. Benefited from an improved source-degenerated architecture, the measured gain error is less than 0.15dB. By adopting the closed-loop architecture and resistor array optimization, the PGA achieves an OIP3 of 19.2dBm and an output P1dB of 7.58dBm. Two methods are implemented for DC-offset cancellation: RC high-pass filter (HPF) and digital-assisted DCOC. Implemented in TSMC 0.18um process, the PGA occupies 0.37mm2 die area and consumes 1.82mA (I and Q path) from a 1.7V supply.
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