R. Farjad-Rad, W. Dally, Hoik-Tiaq Ng, J. Poulton, T. Stone, R. Rathi, E. Lee, D. Huang, R. Nathan
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A 0.2-2 GHz 12 mW multiplying DLL for low-jitter clock synthesis in highly-integrated data communication chips
The MDLL, in 0.18 /spl mu/m CMOS, has 0.05 mm/sup 2/ active area and 200 MHz to 2 GHz speed range. The complete synthesizer, including the output clock buffers, dissipates 12 mW from a 1.8 V supply at 2.0 GHz. This MDLL architecture is used as a clock multiplier in a highly-integrated chip, and has jitter of 1.73 ps (rms) and 15.6 ps (pk-pk) at 2 GHz.
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