电导DLTS分析功率坍落度与栅极滞后的相关性

GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 19th Annual Technical Digest 1997 Pub Date : 1997-10-12 DOI:10.1109/GAAS.1997.628262

R. Leoni, J. Bao, X. Du, M. Shirokov, J.C.M. Hwang

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引用次数: 8

摘要

研究了反向栅极漏极电流应力对GaAs功率MESFET特性的影响。除了先前报道的功率暴跌效应外，门滞后特性变得更糟。应力前后器件的电导dlt测量没有发现新的表面陷阱类型。进一步的研究表明，由于冲击电离的减少，栅极滞后加剧，从而减慢了空穴捕获速率。这证实了钝化过程中的电子陷阱导致了功率下降，而栅极滞后则由于现有表面陷阱对栅极电位的敏感性增加而加剧。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Conductance DLTS analysis of the correlation between power slump and gate lag

Effects of reverse gate-drain current stress on the characteristics of GaAs power MESFET's were investigated. In addition to the previously reported power-slump effect, the gate-lag characteristic became worse. Conductance DLTS measurements of the device before and after stress revealed no new types of surface traps. Further investigation showed gate lag was worsened by a decrease in impact ionization which slowed the hole capture rate. This confirms that power slump is caused by electron traps in the passivation, while gate lag is aggravated by increased sensitivity of existing surface traps to the gate potential.

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GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 19th Annual Technical Digest 1997

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