Using VHDL for simulation of SDL specifications

The authors present the use of VHSIC hardware description language (VHDL) for the simulation of Specification and Description Language (SDL) specification. SDL is a standardized graphical specification and description language. It is widely used for specifications of software systems that are based on message exchange, e.g., telecommunication systems. The approach presented allows for simulation of the logical correctness of the specification, as well as some kinds of performance simulation. A third application of the approach is the joint simulation of hardware and software. The translation of SDL into VHDL allows for functional, performance, and joint hardware/software simulation of systems specified with SDL.<>