A Reconfigurable Processor for Matrix Inversion Computation

this paper proposes a reconfigurable processor for matrix inversion (MI). Two techniques have been proposed for the MI processor: the proposed reconfigurable architecture allows the processor to support different matrix size. The proposed data scaling technique solves the intermediate date size issue, and therefore supports computation of large matrices. For demonstration, the proposed reconfigurable MI processor has been implemented on FPGA. It is able to compute MI for different matrix size with small mean error and short computation time.