Comparative Study of Single MAC FIR Filter Architectures with Different Multiplication Techniques

Emerging technologies in VLSI signal processing systems demand FIR filters' optimal design to support a wide range of applications. This study presents the architectures for single-channel and multichannel FIR filters employing the Time-division multiplexing (TDM) scheme. The studied architecture is associated with one multiplication and addition unit to handle a wide range of channels and filter taps to have efficient resource utilization. Further accumulator-based Radix-4 multiplier, shift and add multiplication, and parallel pipelined multiplication operations involved in the architectures effectively utilize the resources to a considerable extent. The studied 16-tap multiple channel FIR filter design is simulated using Verilog Hardware Description Language (HDL) and synthesis is carried out using Xilinx Vertex Field Programmable Gate Array (FPGA). In addition, single multiply-accumulate (MAC) based FIR filter architectures with different multiplication-based approaches are implemented, and the results are reported. The analysis and synthesis results conclude that the studied 16 taps single MAC FIR structure offers area (slices) optimization of about 89.6% when examining with the conventional Parallel MAC FIR filter structure. Similarly, the 16-tap single MAC multichannel structure offers area (slices) minimization of about 90.01 % over the corresponding parallel MAC multichannel implementation. Further, the single MAC structure with a single-channel employing OPC (Output Product Coding) scheme offers 95% area reduction and 86% speed increment when compared to the parallel MAC structure with single-channel implementation. Also, the single MAC multichannel design with the OPC scheme offers 19.84% SDP (slice delay product) optimization when compared to the other studied architecture.