Takashi Sato, Tadamichi Kozaki, T. Uezono, Hiroshi Tsutsui, H. Ochi
{"title":"一种有效的偏温不稳定性测量装置阵列","authors":"Takashi Sato, Tadamichi Kozaki, T. Uezono, Hiroshi Tsutsui, H. Ochi","doi":"10.1109/ESSDERC.2011.6044214","DOIUrl":null,"url":null,"abstract":"A device array suitable for efficiently collecting statistical information on bias-temperature instability (BTI) parameters of a large number of transistors is presented. The proposed array structure substantially shortens measurement time of threshold voltage shifts under BTI conditions by parallelizing stress periods of multiple devices while maintaining 0.2mV precision. An implementation of BTI array consisting of 128 devices successfully validates stress-pipelining concept. Log-normal distributions of time exponents are experimentally observed.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"28","resultStr":"{\"title\":\"A device array for efficient bias-temperature instability measurements\",\"authors\":\"Takashi Sato, Tadamichi Kozaki, T. Uezono, Hiroshi Tsutsui, H. Ochi\",\"doi\":\"10.1109/ESSDERC.2011.6044214\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A device array suitable for efficiently collecting statistical information on bias-temperature instability (BTI) parameters of a large number of transistors is presented. The proposed array structure substantially shortens measurement time of threshold voltage shifts under BTI conditions by parallelizing stress periods of multiple devices while maintaining 0.2mV precision. An implementation of BTI array consisting of 128 devices successfully validates stress-pipelining concept. Log-normal distributions of time exponents are experimentally observed.\",\"PeriodicalId\":161896,\"journal\":{\"name\":\"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)\",\"volume\":\"4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-10-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"28\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSDERC.2011.6044214\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.2011.6044214","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A device array for efficient bias-temperature instability measurements
A device array suitable for efficiently collecting statistical information on bias-temperature instability (BTI) parameters of a large number of transistors is presented. The proposed array structure substantially shortens measurement time of threshold voltage shifts under BTI conditions by parallelizing stress periods of multiple devices while maintaining 0.2mV precision. An implementation of BTI array consisting of 128 devices successfully validates stress-pipelining concept. Log-normal distributions of time exponents are experimentally observed.