Pratik Nimbalkar, M. Kathaperumal, Fuhan Liu, M. Swaminathan, R. Tummala
{"title":"高密度重分布层微通孔可靠性建模","authors":"Pratik Nimbalkar, M. Kathaperumal, Fuhan Liu, M. Swaminathan, R. Tummala","doi":"10.1109/ECTC32696.2021.00161","DOIUrl":null,"url":null,"abstract":"The ever-increasing demand for high-bandwidth interconnects has given rise to the need for high IO-density package redistribution layers (RDL). This necessitates scaling down RDL critical dimensions as well as microvias. There are numerous challenges pertaining to scaling down microvias below $5\\ \\mu \\mathrm{m}$ diameter. The main challenge is the thermomechanical reliability of vias in polymer dielectrics. Modeling and design for reliability in various polymer dielectrics is the key to achieve mechanical reliability. This paper presents a model for the prediction of micro-via failure. The effects of via geometry such as-via angle and height as well as material properties such as-CTE and elastic modulus on via failure are presented. Furthermore, modeling results are correlated with experimental results to verify the accuracy of the model. Using this model, it was determined that the conventional via geometry reaches an engineering limit at $2 \\mu \\mathrm{m}$ of via diameter. Below this size, it becomes difficult to achieve reliable vias in polymers as they do not survive 1000 thermal cycles. Based on the modeling studies, a novel method is proposed for enhancement of reliability of vias below the engineering limit of $2\\ \\mu \\mathrm{m}$.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Reliability Modeling of Micro-vias in High-Density Redistribution Layers\",\"authors\":\"Pratik Nimbalkar, M. Kathaperumal, Fuhan Liu, M. Swaminathan, R. Tummala\",\"doi\":\"10.1109/ECTC32696.2021.00161\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The ever-increasing demand for high-bandwidth interconnects has given rise to the need for high IO-density package redistribution layers (RDL). This necessitates scaling down RDL critical dimensions as well as microvias. There are numerous challenges pertaining to scaling down microvias below $5\\\\ \\\\mu \\\\mathrm{m}$ diameter. The main challenge is the thermomechanical reliability of vias in polymer dielectrics. Modeling and design for reliability in various polymer dielectrics is the key to achieve mechanical reliability. This paper presents a model for the prediction of micro-via failure. The effects of via geometry such as-via angle and height as well as material properties such as-CTE and elastic modulus on via failure are presented. Furthermore, modeling results are correlated with experimental results to verify the accuracy of the model. Using this model, it was determined that the conventional via geometry reaches an engineering limit at $2 \\\\mu \\\\mathrm{m}$ of via diameter. Below this size, it becomes difficult to achieve reliable vias in polymers as they do not survive 1000 thermal cycles. Based on the modeling studies, a novel method is proposed for enhancement of reliability of vias below the engineering limit of $2\\\\ \\\\mu \\\\mathrm{m}$.\",\"PeriodicalId\":351817,\"journal\":{\"name\":\"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ECTC32696.2021.00161\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC32696.2021.00161","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Reliability Modeling of Micro-vias in High-Density Redistribution Layers
The ever-increasing demand for high-bandwidth interconnects has given rise to the need for high IO-density package redistribution layers (RDL). This necessitates scaling down RDL critical dimensions as well as microvias. There are numerous challenges pertaining to scaling down microvias below $5\ \mu \mathrm{m}$ diameter. The main challenge is the thermomechanical reliability of vias in polymer dielectrics. Modeling and design for reliability in various polymer dielectrics is the key to achieve mechanical reliability. This paper presents a model for the prediction of micro-via failure. The effects of via geometry such as-via angle and height as well as material properties such as-CTE and elastic modulus on via failure are presented. Furthermore, modeling results are correlated with experimental results to verify the accuracy of the model. Using this model, it was determined that the conventional via geometry reaches an engineering limit at $2 \mu \mathrm{m}$ of via diameter. Below this size, it becomes difficult to achieve reliable vias in polymers as they do not survive 1000 thermal cycles. Based on the modeling studies, a novel method is proposed for enhancement of reliability of vias below the engineering limit of $2\ \mu \mathrm{m}$.