{"title":"A236并行DSP芯片提供了经济高效的实时视频处理","authors":"S. G. Morton","doi":"10.1109/ELECTR.1996.501237","DOIUrl":null,"url":null,"abstract":"Oxford Computer's A236 parallel digital signal processor chip is flexible, fully programmable and designed to compactly and inexpensively provide live video capture, processing and display. The use of single-chip, parallel processing with integrated data and instruction caches, and an inexpensive, high performance memory system, provide high performance at low cost. An extended, single-instruction multiple-data (SIMD) architecture with one, 24-bit scalar processor and four, 16-bit vector processors, is used. Five instructions are issued each clock cycle with a 40 MHz clock, providing up to 200 MIPS. Two, 16-bit, bi-directional, double-buffered, DMA ports support simultaneous video acquisition and display, and interface directly to common video decoder and encoder chips with no glue logic. A minimum system that provides all input and output frame buffering contains only three chips, an A236 Chip, a 32-bit wide, synchronous DRAM, and a serial I/sup 2/C EEPROM, plus analog video interface chips. A full set of software development tools that runs under MS Windows is available free, including an enhanced C-compiler that provides a simple method for representing parallel operations on data structures. An evaluation kit containing the software tools and the A236 Video Processing System I is also available.","PeriodicalId":119154,"journal":{"name":"Professional Program Proceedings. ELECTRO '96","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A236 parallel DSP chip provides real-time video processing economically and efficiently\",\"authors\":\"S. G. Morton\",\"doi\":\"10.1109/ELECTR.1996.501237\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Oxford Computer's A236 parallel digital signal processor chip is flexible, fully programmable and designed to compactly and inexpensively provide live video capture, processing and display. The use of single-chip, parallel processing with integrated data and instruction caches, and an inexpensive, high performance memory system, provide high performance at low cost. An extended, single-instruction multiple-data (SIMD) architecture with one, 24-bit scalar processor and four, 16-bit vector processors, is used. Five instructions are issued each clock cycle with a 40 MHz clock, providing up to 200 MIPS. Two, 16-bit, bi-directional, double-buffered, DMA ports support simultaneous video acquisition and display, and interface directly to common video decoder and encoder chips with no glue logic. A minimum system that provides all input and output frame buffering contains only three chips, an A236 Chip, a 32-bit wide, synchronous DRAM, and a serial I/sup 2/C EEPROM, plus analog video interface chips. A full set of software development tools that runs under MS Windows is available free, including an enhanced C-compiler that provides a simple method for representing parallel operations on data structures. An evaluation kit containing the software tools and the A236 Video Processing System I is also available.\",\"PeriodicalId\":119154,\"journal\":{\"name\":\"Professional Program Proceedings. ELECTRO '96\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-04-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Professional Program Proceedings. ELECTRO '96\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ELECTR.1996.501237\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Professional Program Proceedings. ELECTRO '96","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ELECTR.1996.501237","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A236 parallel DSP chip provides real-time video processing economically and efficiently
Oxford Computer's A236 parallel digital signal processor chip is flexible, fully programmable and designed to compactly and inexpensively provide live video capture, processing and display. The use of single-chip, parallel processing with integrated data and instruction caches, and an inexpensive, high performance memory system, provide high performance at low cost. An extended, single-instruction multiple-data (SIMD) architecture with one, 24-bit scalar processor and four, 16-bit vector processors, is used. Five instructions are issued each clock cycle with a 40 MHz clock, providing up to 200 MIPS. Two, 16-bit, bi-directional, double-buffered, DMA ports support simultaneous video acquisition and display, and interface directly to common video decoder and encoder chips with no glue logic. A minimum system that provides all input and output frame buffering contains only three chips, an A236 Chip, a 32-bit wide, synchronous DRAM, and a serial I/sup 2/C EEPROM, plus analog video interface chips. A full set of software development tools that runs under MS Windows is available free, including an enhanced C-compiler that provides a simple method for representing parallel operations on data structures. An evaluation kit containing the software tools and the A236 Video Processing System I is also available.