{"title":"BiCMOS卡开故障检测的可测试设计","authors":"S. Menon, A. Jayasumana, Y. Malaiya","doi":"10.1109/VTEST.1993.313362","DOIUrl":null,"url":null,"abstract":"BiCMOS devices exhibit sequential behavior under transistor stuck-open (s-open) faults. In addition to the sequential behavior, delay faults are also present. Detection of s-open faults exhibiting sequential behavior need two or multipattern sequences, and delay faults are all the more difficult to detect. A new design for testability scheme is presented for single BJT BiCMOS logic gates which uses only two extra transistors to improve the circuit testability regardless of timing skews/delays, glitches or charge sharing among internal nodes. It requires only a single vector instead of the two or multipattern sequences. The testable design scheme presented also avoids the requirement of generating tests for delay faults.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Testable design for BiCMOS stuck-open fault detection\",\"authors\":\"S. Menon, A. Jayasumana, Y. Malaiya\",\"doi\":\"10.1109/VTEST.1993.313362\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"BiCMOS devices exhibit sequential behavior under transistor stuck-open (s-open) faults. In addition to the sequential behavior, delay faults are also present. Detection of s-open faults exhibiting sequential behavior need two or multipattern sequences, and delay faults are all the more difficult to detect. A new design for testability scheme is presented for single BJT BiCMOS logic gates which uses only two extra transistors to improve the circuit testability regardless of timing skews/delays, glitches or charge sharing among internal nodes. It requires only a single vector instead of the two or multipattern sequences. The testable design scheme presented also avoids the requirement of generating tests for delay faults.<<ETX>>\",\"PeriodicalId\":283218,\"journal\":{\"name\":\"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium\",\"volume\":\"13 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-04-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VTEST.1993.313362\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTEST.1993.313362","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Testable design for BiCMOS stuck-open fault detection
BiCMOS devices exhibit sequential behavior under transistor stuck-open (s-open) faults. In addition to the sequential behavior, delay faults are also present. Detection of s-open faults exhibiting sequential behavior need two or multipattern sequences, and delay faults are all the more difficult to detect. A new design for testability scheme is presented for single BJT BiCMOS logic gates which uses only two extra transistors to improve the circuit testability regardless of timing skews/delays, glitches or charge sharing among internal nodes. It requires only a single vector instead of the two or multipattern sequences. The testable design scheme presented also avoids the requirement of generating tests for delay faults.<>