A 5-bit 1.5 GS/s ADC using reduced comparator architecture

Recent trends in mixed-signal design for wireless application require high speed, power-efficient ADCs. Flash ADC architecture is an optimum choice for speed but dissipates power exponentially with increase in resolution. The present work on 5-bit 1.5 GS/s ADC explores new architectural strategy of circuit design in optimizing the power using reduced comparator architecture. The proposed circuit using only 5 comparators when operated with 2.5 V supply, dissipates less (83mW) power and silicon area as compared to existing architectures. The proposed ADC offers an ENOB of 4.60 bits, SNR of 27.2dB, SFDR of 36.21dB, INL and DNL of 0.32L5B and 0.43L5B respectively when simulated using 500nm CMOS MOSIS (AMIS) C5X design kit.