soc的制造测试

R. Kapur, T. Williams
{"title":"soc的制造测试","authors":"R. Kapur, T. Williams","doi":"10.1109/ATS.2002.1181730","DOIUrl":null,"url":null,"abstract":"In this paper the solution the industry is driving towards for manufacturing test of SoCs is described. The quality of test for every core that is integrated on the chip is very important to the overall quality of the SoC. In this paper a method for evaluating the quality needs of an embedded core relative to the embedded environment is presented. Due to the partitioning of the test data and the increased stress in quality for individual designs the test application time is increasing. This paper presents the problems associated with test application time with SoCs.","PeriodicalId":199542,"journal":{"name":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"Manufacturing test of SoCs\",\"authors\":\"R. Kapur, T. Williams\",\"doi\":\"10.1109/ATS.2002.1181730\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper the solution the industry is driving towards for manufacturing test of SoCs is described. The quality of test for every core that is integrated on the chip is very important to the overall quality of the SoC. In this paper a method for evaluating the quality needs of an embedded core relative to the embedded environment is presented. Due to the partitioning of the test data and the increased stress in quality for individual designs the test application time is increasing. This paper presents the problems associated with test application time with SoCs.\",\"PeriodicalId\":199542,\"journal\":{\"name\":\"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).\",\"volume\":\"14 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-11-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS.2002.1181730\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.2002.1181730","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9

摘要

本文描述了业界正在推动的soc制造测试解决方案。芯片上集成的每个核心的测试质量对SoC的整体质量非常重要。本文提出了一种评估嵌入式核心相对于嵌入式环境的质量需求的方法。由于测试数据的分割和单个设计的质量压力的增加,测试应用时间正在增加。本文介绍了与soc测试应用时间相关的问题。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
Manufacturing test of SoCs
In this paper the solution the industry is driving towards for manufacturing test of SoCs is described. The quality of test for every core that is integrated on the chip is very important to the overall quality of the SoC. In this paper a method for evaluating the quality needs of an embedded core relative to the embedded environment is presented. Due to the partitioning of the test data and the increased stress in quality for individual designs the test application time is increasing. This paper presents the problems associated with test application time with SoCs.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Time slot specification based approach to analog fault diagnosis using built-in current sensors and test point insertion Efficient circuit specific pseudoexhaustive testing with cellular automata A ROMless LFSR reseeding scheme for scan-based BIST A fault-tolerant architecture for symmetric block ciphers High precision result evaluation of VLSI
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1