{"title":"用于超高密度封装和3D电路集成的陶瓷中间体","authors":"A. Adibi, A. Isapour, Mohsen Niayesh, A. Kouki","doi":"10.1109/EPTC.2018.8654283","DOIUrl":null,"url":null,"abstract":"Higher data speeds spurred on by the arrival of 5G technology and the Internet of Things (IoT) have accelerated the need for increased circuit integration with shorter interconnects. 3D integration and packaging techniques that employ silicon interposers with Through Silicon Vias (TSVs) have emerged as one of the key technologies in enabling this trend. In this paper, a cost-effective alternative to silicon interposers based on Low Temperature Co-fired Ceramic (LTCC) technology is proposed and demonstrated. Using ultra-thin ceramic layers and laser ablation, ceramic interposers with micro-via holes as small as $20 \\mu \\mathrm{m}$ in diameter and $40 \\mu \\mathrm{m}$ pitch have been successfully realized. In addition to the standalone interposers, the developed fabrication process has been used to design a high-density package for the integration of Silicon Photonic (SiP) and electronic chips with operational bandwidth up to 48 GHz. This novel cost-effective packaging technology offers a viable alternative to silicon interposers for the integration of multi-chip high-speed electronic systems in a single package with high reliability and very good performance to maintain signal integrity.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Ceramic Interposers for Ultra-High Density Packaging and 3D Circuit Integration\",\"authors\":\"A. Adibi, A. Isapour, Mohsen Niayesh, A. Kouki\",\"doi\":\"10.1109/EPTC.2018.8654283\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Higher data speeds spurred on by the arrival of 5G technology and the Internet of Things (IoT) have accelerated the need for increased circuit integration with shorter interconnects. 3D integration and packaging techniques that employ silicon interposers with Through Silicon Vias (TSVs) have emerged as one of the key technologies in enabling this trend. In this paper, a cost-effective alternative to silicon interposers based on Low Temperature Co-fired Ceramic (LTCC) technology is proposed and demonstrated. Using ultra-thin ceramic layers and laser ablation, ceramic interposers with micro-via holes as small as $20 \\\\mu \\\\mathrm{m}$ in diameter and $40 \\\\mu \\\\mathrm{m}$ pitch have been successfully realized. In addition to the standalone interposers, the developed fabrication process has been used to design a high-density package for the integration of Silicon Photonic (SiP) and electronic chips with operational bandwidth up to 48 GHz. This novel cost-effective packaging technology offers a viable alternative to silicon interposers for the integration of multi-chip high-speed electronic systems in a single package with high reliability and very good performance to maintain signal integrity.\",\"PeriodicalId\":360239,\"journal\":{\"name\":\"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)\",\"volume\":\"21 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EPTC.2018.8654283\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPTC.2018.8654283","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Ceramic Interposers for Ultra-High Density Packaging and 3D Circuit Integration
Higher data speeds spurred on by the arrival of 5G technology and the Internet of Things (IoT) have accelerated the need for increased circuit integration with shorter interconnects. 3D integration and packaging techniques that employ silicon interposers with Through Silicon Vias (TSVs) have emerged as one of the key technologies in enabling this trend. In this paper, a cost-effective alternative to silicon interposers based on Low Temperature Co-fired Ceramic (LTCC) technology is proposed and demonstrated. Using ultra-thin ceramic layers and laser ablation, ceramic interposers with micro-via holes as small as $20 \mu \mathrm{m}$ in diameter and $40 \mu \mathrm{m}$ pitch have been successfully realized. In addition to the standalone interposers, the developed fabrication process has been used to design a high-density package for the integration of Silicon Photonic (SiP) and electronic chips with operational bandwidth up to 48 GHz. This novel cost-effective packaging technology offers a viable alternative to silicon interposers for the integration of multi-chip high-speed electronic systems in a single package with high reliability and very good performance to maintain signal integrity.