Vassilis Alimisis, P. Bertsias, C. Psychalinos, A. Elwakil
{"title":"动脉粘弹性模型的电子可调实现","authors":"Vassilis Alimisis, P. Bertsias, C. Psychalinos, A. Elwakil","doi":"10.1109/TSP.2019.8768898","DOIUrl":null,"url":null,"abstract":"A fractional-order implementation of the model of the arterial viscoelasticity is presented in this work. The main attractive offered benefit is that all the states of the arterial viscoelasticity are implemented by the same core, just by adjusting appropriate dc bias currents. This has been achieved through the proposal of an enhanced fractional-order inductor emulator, where the characteristics of the element can be independently adjusted. The behavior of the designed model has been evaluated through post-layout simulation results, using the Cadence IC design suite and the Design Kit provided by the Austria Mikro Systeme (AMS) 0.35μm CMOS process.","PeriodicalId":399087,"journal":{"name":"2019 42nd International Conference on Telecommunications and Signal Processing (TSP)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Electronically Tunable Implementation of the Arterial Viscoelasticity Model\",\"authors\":\"Vassilis Alimisis, P. Bertsias, C. Psychalinos, A. Elwakil\",\"doi\":\"10.1109/TSP.2019.8768898\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A fractional-order implementation of the model of the arterial viscoelasticity is presented in this work. The main attractive offered benefit is that all the states of the arterial viscoelasticity are implemented by the same core, just by adjusting appropriate dc bias currents. This has been achieved through the proposal of an enhanced fractional-order inductor emulator, where the characteristics of the element can be independently adjusted. The behavior of the designed model has been evaluated through post-layout simulation results, using the Cadence IC design suite and the Design Kit provided by the Austria Mikro Systeme (AMS) 0.35μm CMOS process.\",\"PeriodicalId\":399087,\"journal\":{\"name\":\"2019 42nd International Conference on Telecommunications and Signal Processing (TSP)\",\"volume\":\"26 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-07-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 42nd International Conference on Telecommunications and Signal Processing (TSP)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TSP.2019.8768898\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 42nd International Conference on Telecommunications and Signal Processing (TSP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TSP.2019.8768898","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Electronically Tunable Implementation of the Arterial Viscoelasticity Model
A fractional-order implementation of the model of the arterial viscoelasticity is presented in this work. The main attractive offered benefit is that all the states of the arterial viscoelasticity are implemented by the same core, just by adjusting appropriate dc bias currents. This has been achieved through the proposal of an enhanced fractional-order inductor emulator, where the characteristics of the element can be independently adjusted. The behavior of the designed model has been evaluated through post-layout simulation results, using the Cadence IC design suite and the Design Kit provided by the Austria Mikro Systeme (AMS) 0.35μm CMOS process.