VLSI电路中的延迟和功率优化

21st Design Automation Conference Proceedings Pub Date : 1984-06-25 DOI:10.1109/DAC.1984.1585848

L. Glasser, L. Hoyte

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引用次数: 80

摘要

研究了数字MOS VLSI电路中晶体管的最佳尺寸问题。建立了宏观模型，提出了关键路径上晶体管最优尺寸的新定理。讨论了设计自动化程序进行优化的结果。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Delay and Power Optimization in VLSI Circuits

The problem of optimally sizing the transistors in a digital MOS VLSI circuit is examined. Macro-models are developed and new theorems on the optimal sizing of the transistors in a critical path are presented. The results of a design automation procedure to perform the optimization is discussed.

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21st Design Automation Conference Proceedings

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