Colin D. Renfrew, Brian Booth, Shweta Latawa, R. Woltenberg, C. Pyron
{"title":"在QorIQTM P2020平台上进行高速测试","authors":"Colin D. Renfrew, Brian Booth, Shweta Latawa, R. Woltenberg, C. Pyron","doi":"10.1109/TEST.2009.5355588","DOIUrl":null,"url":null,"abstract":"This paper describes how at-speed testing for delay faults was achieved on the P2020 QorIQ device. Modifications to the scan clocking architecture were made over previous designs in order to facilitate at-speed testing and improve overall test coverage. A methodology for ATPG was derived for this enhanced architecture and applied to the device. The design and implementation will be presented in this paper, along with results from ATPG and silicon.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"177 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"At-speed test on the QorIQTM P2020 platform\",\"authors\":\"Colin D. Renfrew, Brian Booth, Shweta Latawa, R. Woltenberg, C. Pyron\",\"doi\":\"10.1109/TEST.2009.5355588\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes how at-speed testing for delay faults was achieved on the P2020 QorIQ device. Modifications to the scan clocking architecture were made over previous designs in order to facilitate at-speed testing and improve overall test coverage. A methodology for ATPG was derived for this enhanced architecture and applied to the device. The design and implementation will be presented in this paper, along with results from ATPG and silicon.\",\"PeriodicalId\":419063,\"journal\":{\"name\":\"2009 International Test Conference\",\"volume\":\"177 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-12-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 International Test Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TEST.2009.5355588\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Test Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.2009.5355588","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper describes how at-speed testing for delay faults was achieved on the P2020 QorIQ device. Modifications to the scan clocking architecture were made over previous designs in order to facilitate at-speed testing and improve overall test coverage. A methodology for ATPG was derived for this enhanced architecture and applied to the device. The design and implementation will be presented in this paper, along with results from ATPG and silicon.
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