Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions

Electrostatically controlled graphene p-n junctions are devices built on single-layer graphene sheets whose in-to-out resistance can be dynamically tuned through external voltage potentials. While several recent works mainly focused on the possibility of using those devices as a new logic primitive for digital circuits, in this paper we address a complementary problem, that is, how to efficiently implement Analog-to-Digital Converters (ADCs) that can be integrated in future all-graphene flexible ICs. The contribution of this work is threefold: (i) introduce a new ADC architecture that perfectly matches with the main characteristics of graphene p-n junctions; (ii) give a first, yet detailed parametric characterization of the proposed ADC architecture as to validate its functionality and quantify its figures of merit; (iii) provide a fully automated design flow that, given as input the design specs, i.e., input voltage range, voltage resolution and sampling rate, returns an optimally sized ADC circuitry. Few case studies also demonstrate p-n junction based graphene ADCs have characteristics in line with those offered by todays' CMOS ones.