K. Sagara, T. Kure, S. Shukuri, J. Yugami, N. Hasegawa, H. Shinriki, H. Goto, H. Yamashita, E. Takeda
{"title":"采用四分之一微米相移光刻技术的256 Mbit dram的0.72 μ m/sup /嵌入式STC (RSTC)技术","authors":"K. Sagara, T. Kure, S. Shukuri, J. Yugami, N. Hasegawa, H. Shinriki, H. Goto, H. Yamashita, E. Takeda","doi":"10.1109/VLSIT.1992.200618","DOIUrl":null,"url":null,"abstract":"A recessed stacked capacitor (RSTC) structure to achieve both fine-pattern delineation and high cell capacitance is presented. Using a RSTC structure, an experimental memory array with 0.25 mu m phase-shift lithography and CVD-W plate technology has been fabricated. A 25-fF/cell capacitance was obtained in a 0.72 mu m/sup 2/ cell.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"A 0.72 mu m/sup 2/ recessed STC (RSTC) technology for 256 Mbit DRAMs using quarter-micron phase-shift lithography\",\"authors\":\"K. Sagara, T. Kure, S. Shukuri, J. Yugami, N. Hasegawa, H. Shinriki, H. Goto, H. Yamashita, E. Takeda\",\"doi\":\"10.1109/VLSIT.1992.200618\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A recessed stacked capacitor (RSTC) structure to achieve both fine-pattern delineation and high cell capacitance is presented. Using a RSTC structure, an experimental memory array with 0.25 mu m phase-shift lithography and CVD-W plate technology has been fabricated. A 25-fF/cell capacitance was obtained in a 0.72 mu m/sup 2/ cell.<<ETX>>\",\"PeriodicalId\":404756,\"journal\":{\"name\":\"1992 Symposium on VLSI Technology Digest of Technical Papers\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-06-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1992 Symposium on VLSI Technology Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.1992.200618\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1992 Symposium on VLSI Technology Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1992.200618","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 0.72 mu m/sup 2/ recessed STC (RSTC) technology for 256 Mbit DRAMs using quarter-micron phase-shift lithography
A recessed stacked capacitor (RSTC) structure to achieve both fine-pattern delineation and high cell capacitance is presented. Using a RSTC structure, an experimental memory array with 0.25 mu m phase-shift lithography and CVD-W plate technology has been fabricated. A 25-fF/cell capacitance was obtained in a 0.72 mu m/sup 2/ cell.<>
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