通过参数化各种进位传播子加法器块的位宽,在扩展的加法器结构设计空间中实现更好的面积-时间权衡

Jeong-Gun Lee, Jeong-A Lee, Deok-Young Lee
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引用次数: 4

摘要

有许多加法器设计供设计人员选择最快或最小或最节能的加法器。然而,现有加法器的性能在速度和面积要求上差异很大,这反过来有时会使设计人员在面积上付出高昂的代价,特别是当延迟要求超过特定加法器的最快速度时,无论差异有多小。为了消除成本的增加,我们提出了具有扩展设计空间的新加法器架构,以实现更好的设计权衡。这种新的加法器结构被称为变异加法器结构,它用各种进位传播加法器块作为子加法器组件来重构加法器,以帮助设计者选择具有有利特性的加法器。给出了整数线性规划中各种进位传播分量加法器位宽的确定问题。我们使用128位加法器设计证明了新加法器架构的有效性
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Better Area-Time Tradeoffs in an Expanded Design Space of Adder Architecture by Parameterizing Bit-width of Various Carry Propagated Sub-adder-blocks
Many adder designs exist for a designer to choose the fastest or the smallest or power efficient one. However, the performance of existing adders varies widely in their speed and area requirements, which in turn sometimes makes designers pay a high cost in area especially when the delay requirements exceeds the fastest speed of a specific adder, no matter how small the difference it is. To smooth such an increase in cost, we propose new adder architecture with expanded design space for better design tradeoffs. The new adder architecture, named a mutated adder architecture, restructures an adder with blocks of various carry propagated adders as sub-adder-components to aid a designer in selecting his/her adder with favorable characteristics. We formulate the problem of determining the bit-width of various carry propagate component adders in integer linear programming. We demonstrate the effectiveness of the new adder architecture using 128-bit adder design
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