Studies on a novel flip-chip interconnect structure. Pillar bump

Pillar bump is a novel interconnect structure, including non-reflowable base and a reflowable cap like a pillar shape. In this study, pillar bump with copper base and Sn63/Pb37 eutectic solder cap is processed via electrolytic plating. Based on whether flat eutectic cap is reflowed prior to assembly, pillar bump is further split into two categories, namely pre-reflowed and non-reflowed, respectively. Assembly feasibility assessment as well as bump integrity evaluation are carried out. Bump shear test is conducted for both before and after reliability and failure mode is characterized via SEM and EDX. Furthermore, a 10 mm/spl times/10 mm test chip having 180 Cu/eutectic solder pillar bumps with 0.2 mm pitch is assembled onto BT substrate via no clean flux and subsequently underfilled. The results show that pillar shape is still maintained after assembly that can meet fine pitch requirement. No shear strength deterioration after moisture sensitivity preconditioning and 1000 thermal cycle test (TCT, -40/spl deg/C/spl sim/125/spl deg/C) has been observed. EDX spectra indicate fracture has occurred in the interfacial region between Al and silicon, not arising from bumping process. Furthermore, bump integrity is intact after package level reliability test under the same conditions as above. Stress simulation results lead to conclusion that maximum shear stress occurs in copper pillar portion with average range of 40/spl sim/50 MPa that is much below the shear strength of copper.