Maximal reduction of lookup-table based FPGAs

Field programmable gate array (FPGA) is an important VLSI technology. Many algorithms have been proposed for the synthesis of FPGAs, but most of them concern issues in technology-mapping. The authors present a new logic minimization algorithm MR (maximal reduction) for the minimization of FPGA networks using lookup-tables. Information is obtained on how to remove the lookup tables by using network resynthesis techniques. Order-independent and global optimal results are obtained by formulating the lookup-table minimization problem as a maximum independent set problem. Experimental results show that MR can significantly improve the designs obtained by existing FPGA synthesis algorithms.<>