Mohamad Kazem Anvarifard, M. G. Armaki, S. E. Hosseini
{"title":"一种新型双栅SOI晶体管和减少短通道效应的证据","authors":"Mohamad Kazem Anvarifard, M. G. Armaki, S. E. Hosseini","doi":"10.1109/ELECTRO.2009.5441180","DOIUrl":null,"url":null,"abstract":"In this paper a new transistor of dual-gate (DG) silicon-on- insulator (SOI) MOSFET is presented. The objects of this paper are to use a voltage difference between the two gates to screen the drain voltage and therefore reduce short channel effects (SCEs). In this transistor the surface potential exhibits a step function, which causes the screening of the drain potential. This results in suppressed SCEs such as the hot-carrier effect and decreasing off-current with respect to shrinking of channel length. The obtained results of our transistor are compared to single gate (SG) SOI MOSFET that shows the DG SOI MOSFET performance is superior. The transistor has been simulated by SILVACO software.","PeriodicalId":149384,"journal":{"name":"2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A new transistor of dual-gate SOI and evidence for diminished short channel effects\",\"authors\":\"Mohamad Kazem Anvarifard, M. G. Armaki, S. E. Hosseini\",\"doi\":\"10.1109/ELECTRO.2009.5441180\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper a new transistor of dual-gate (DG) silicon-on- insulator (SOI) MOSFET is presented. The objects of this paper are to use a voltage difference between the two gates to screen the drain voltage and therefore reduce short channel effects (SCEs). In this transistor the surface potential exhibits a step function, which causes the screening of the drain potential. This results in suppressed SCEs such as the hot-carrier effect and decreasing off-current with respect to shrinking of channel length. The obtained results of our transistor are compared to single gate (SG) SOI MOSFET that shows the DG SOI MOSFET performance is superior. The transistor has been simulated by SILVACO software.\",\"PeriodicalId\":149384,\"journal\":{\"name\":\"2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems\",\"volume\":\"20 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ELECTRO.2009.5441180\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ELECTRO.2009.5441180","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
摘要
本文提出了一种新型的双栅绝缘子上硅MOSFET晶体管。本文的目标是利用两个栅极之间的电压差来屏蔽漏极电压，从而减少短通道效应(SCEs)。在这种晶体管中，表面电势呈阶跃函数，导致漏极电势的屏蔽。这导致抑制ses，如热载子效应和减少的关断电流相对于通道长度的缩小。将所得结果与单栅SOI MOSFET进行了比较，结果表明DG SOI MOSFET的性能更优越。利用SILVACO软件对该晶体管进行了仿真。
A new transistor of dual-gate SOI and evidence for diminished short channel effects
In this paper a new transistor of dual-gate (DG) silicon-on- insulator (SOI) MOSFET is presented. The objects of this paper are to use a voltage difference between the two gates to screen the drain voltage and therefore reduce short channel effects (SCEs). In this transistor the surface potential exhibits a step function, which causes the screening of the drain potential. This results in suppressed SCEs such as the hot-carrier effect and decreasing off-current with respect to shrinking of channel length. The obtained results of our transistor are compared to single gate (SG) SOI MOSFET that shows the DG SOI MOSFET performance is superior. The transistor has been simulated by SILVACO software.
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