一种有效的fpga时序驱动精细布局算法

Shounak Dhar, M. Iyer, Saurabh N. Adya, L. Singhal, N. Rubanov, D. Pan
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引用次数: 8

摘要

本文提出了一种基于关键路径优化的fpga时序驱动精细布局技术。我们的方法远远超出了以前已知的关键路径优化方法,并探索了更大的解决方案空间。它也是对基于单网的时间优化方法的补充。该算法将详细的布局改进问题建模为最短路径优化问题,同时优化整个定时关键路径中所有元素的布局,同时使相邻非关键元素的布局调整成本最小化。在工业电路上使用现代FPGA器件的实验结果表明,平均放置时钟频率提高了4.5%。
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An Effective Timing-Driven Detailed Placement Algorithm for FPGAs
In this paper, we propose a new timing-driven detailed placement technique for FPGAs based on optimizing critical paths. Our approach extends well beyond the previously known critical path optimization approaches and explores a significantly larger solution space. It is also complementary to single-net based timing optimization approaches. The new algorithm models the detailed placement improvement problem as a shortest path optimization problem, and optimizes the placement of all elements in the entire timing critical path simultaneously, while minimizing the costs of adjusting the placement of adjacent non-critical elements. Experimental results on industrial circuits using a modern FPGA device show an average placement clock frequency improvement of 4.5%.
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