GaAs VLSI技术的工艺、性能和可靠性表征

W. Yamada, K. Macwilliams, S. Brown, N. Zamani, B. Blaes, M. Buehler
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引用次数: 1

摘要

作者介绍了对商业数字GaAs铸造厂的研究结果,并试图建立一种方法来表征该铸造厂技术的过程、性能和可靠性。设计了各种日益复杂的测试结构来表征数字砷化镓工艺。这些结构包括互连、触点、结和器件的基本测试结构,以日益复杂的门、锁存器、简单电路和门阵列。越来越复杂的测试结构保证了测试结果的一致性和准确性。一种称为矩阵延迟链的新型定时电路是表征该技术的关键结构之一。这种测试结构的目的是允许直接测量逆变器的传播延迟,并作为性能变化的监测。这些变化是由于(1)工艺不均匀性,(2)电源波动,(3)极端温度,(4)可靠性下降(用于空间)和(5)辐射退化。测试结构采用增强-耗尽模式工艺,栅极长度为0.8 /spl mu/m,铝基金属化为三层
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Process, performance, and reliability characterization of a GaAs VLSI technology
The authors present the results from a study of a commercial digital GaAs foundry and attempt to establish a methodology to characterize the process, performance, and reliability of that foundry's technology. A variety of increasingly complex test structures were designed to characterize the digital GaAs process. These structures include the elemental test structures for interconnects, contacts, junctions and devices to increasingly complex gates, latches, simple circuits and gate arrays. The increasing complexity in test structures insures that the results obtained are consistent and accurate. A novel timing circuit called a matrix delay chain is one of the key structures used to characterize the technology. This test structure is intended to allow the direct measurement of inverter propagation delay and as a monitor of performance variations. These variations are due to (1) process nonuniformities, (2) power supply fluctuations, (3) temperature extremes, (4) reliability degradations and, for use in space, and (5) radiation degradations. The collection of test structures was fabricated in an enhancement-depletion mode process utilizing 0.8 /spl mu/m gate length, and three level aluminum based metallization.<>
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