W. Yamada, K. Macwilliams, S. Brown, N. Zamani, B. Blaes, M. Buehler
{"title":"GaAs VLSI技术的工艺、性能和可靠性表征","authors":"W. Yamada, K. Macwilliams, S. Brown, N. Zamani, B. Blaes, M. Buehler","doi":"10.1109/GAAS.1993.394490","DOIUrl":null,"url":null,"abstract":"The authors present the results from a study of a commercial digital GaAs foundry and attempt to establish a methodology to characterize the process, performance, and reliability of that foundry's technology. A variety of increasingly complex test structures were designed to characterize the digital GaAs process. These structures include the elemental test structures for interconnects, contacts, junctions and devices to increasingly complex gates, latches, simple circuits and gate arrays. The increasing complexity in test structures insures that the results obtained are consistent and accurate. A novel timing circuit called a matrix delay chain is one of the key structures used to characterize the technology. This test structure is intended to allow the direct measurement of inverter propagation delay and as a monitor of performance variations. These variations are due to (1) process nonuniformities, (2) power supply fluctuations, (3) temperature extremes, (4) reliability degradations and, for use in space, and (5) radiation degradations. The collection of test structures was fabricated in an enhancement-depletion mode process utilizing 0.8 /spl mu/m gate length, and three level aluminum based metallization.<<ETX>>","PeriodicalId":347339,"journal":{"name":"15th Annual GaAs IC Symposium","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Process, performance, and reliability characterization of a GaAs VLSI technology\",\"authors\":\"W. Yamada, K. Macwilliams, S. Brown, N. Zamani, B. Blaes, M. Buehler\",\"doi\":\"10.1109/GAAS.1993.394490\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The authors present the results from a study of a commercial digital GaAs foundry and attempt to establish a methodology to characterize the process, performance, and reliability of that foundry's technology. A variety of increasingly complex test structures were designed to characterize the digital GaAs process. These structures include the elemental test structures for interconnects, contacts, junctions and devices to increasingly complex gates, latches, simple circuits and gate arrays. The increasing complexity in test structures insures that the results obtained are consistent and accurate. A novel timing circuit called a matrix delay chain is one of the key structures used to characterize the technology. This test structure is intended to allow the direct measurement of inverter propagation delay and as a monitor of performance variations. These variations are due to (1) process nonuniformities, (2) power supply fluctuations, (3) temperature extremes, (4) reliability degradations and, for use in space, and (5) radiation degradations. The collection of test structures was fabricated in an enhancement-depletion mode process utilizing 0.8 /spl mu/m gate length, and three level aluminum based metallization.<<ETX>>\",\"PeriodicalId\":347339,\"journal\":{\"name\":\"15th Annual GaAs IC Symposium\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-10-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"15th Annual GaAs IC Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/GAAS.1993.394490\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"15th Annual GaAs IC Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GAAS.1993.394490","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Process, performance, and reliability characterization of a GaAs VLSI technology
The authors present the results from a study of a commercial digital GaAs foundry and attempt to establish a methodology to characterize the process, performance, and reliability of that foundry's technology. A variety of increasingly complex test structures were designed to characterize the digital GaAs process. These structures include the elemental test structures for interconnects, contacts, junctions and devices to increasingly complex gates, latches, simple circuits and gate arrays. The increasing complexity in test structures insures that the results obtained are consistent and accurate. A novel timing circuit called a matrix delay chain is one of the key structures used to characterize the technology. This test structure is intended to allow the direct measurement of inverter propagation delay and as a monitor of performance variations. These variations are due to (1) process nonuniformities, (2) power supply fluctuations, (3) temperature extremes, (4) reliability degradations and, for use in space, and (5) radiation degradations. The collection of test structures was fabricated in an enhancement-depletion mode process utilizing 0.8 /spl mu/m gate length, and three level aluminum based metallization.<>