The Analog Front End of Ultra-High Resolution CCD Design Based on AD9920A

A kind of the analog front end design method for the ultra-high resolution CCD was put forward. According to characteristics of CCD KAF-39000 in the still capture, the CCD driver state flow was designed. Two AD9920A chips were used to digitize right and left half frames of the analog image synchronously. One AD9920A which was as the master timing controller generated programmable horizontal and vertical driver clocks for KAF-39000. These driver clocks were made up of four class timing patterns based on AD9920A. FPGA converted AD9920A output clocks to standard digital image interface clocks for digital image acquisition. Experiments show that the AFE circuit system can output good raw image, its frame time, output noise and the dynamic range are 1100ms, 2.12@12bit and 65.7dB, respectively. The Bayer Color image is reconstructed in the FPGA by the color interpolation algorithm based on color difference space and edge detection technique. With better flexibility and extendibility, this design method can be widely used in more ultra-high resolution imaging fields like remote sensing detection and optical measuring.