Ziyue Zhang, Yingtao Ding, Lei Xiao, Ziru Cai, Baoyan Yang, Zhaohu Wu, Yuwen Su, Zhiming Chen
{"title":"小直径超高纵横比通硅孔(tsv)中铜种子层的研制","authors":"Ziyue Zhang, Yingtao Ding, Lei Xiao, Ziru Cai, Baoyan Yang, Zhaohu Wu, Yuwen Su, Zhiming Chen","doi":"10.1109/ECTC32696.2021.00300","DOIUrl":null,"url":null,"abstract":"Through-silicon-vias (TSVs) with high aspect ratio are of great demand due to their advantages in high density three-dimensional (3D) integration. This paper presents a feasible and convenient process flow for fabricating insulation layer, barrier and seed layer in ultra-high aspect ratio TSVs. A conformal polyimide (PI) liner is deposited by vacuum-assisted spin coating technique. Then a uniform TiN barrier layer is fabricated using atomic layer deposition (ALD) at 270 °C. The seed layer is fabricated by sequentially applying sputtering and electroless plating of Cu. Notably, with the pre-treatment effect of sputtered Cu, the electroless plating process is able to form a continuous Cu layer in high aspect ratio vias. Dense and continuous Cu seed layers are successfully fabricated in TSVs with diameters of 3 µm and 5 µm, respectively. The aspect ratios of the TSVs are larger than 17. The minimum thickness of the Cu seed layer inside TSVs is around 100 nm, and such a continuous seed layer is beneficial to the subsequent electroplating of Cu conductor. The proposed process flow for the formation of liner, barrier and seed layer in ultra-high aspect ratio TSVs is useful for the fabrication of interconnects in heterogeneous integration of various modern electronic systems and devices.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Development of Cu Seed Layers in Ultra-High Aspect Ratio Through-Silicon-Vias (TSVs) with Small Diameters\",\"authors\":\"Ziyue Zhang, Yingtao Ding, Lei Xiao, Ziru Cai, Baoyan Yang, Zhaohu Wu, Yuwen Su, Zhiming Chen\",\"doi\":\"10.1109/ECTC32696.2021.00300\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Through-silicon-vias (TSVs) with high aspect ratio are of great demand due to their advantages in high density three-dimensional (3D) integration. This paper presents a feasible and convenient process flow for fabricating insulation layer, barrier and seed layer in ultra-high aspect ratio TSVs. A conformal polyimide (PI) liner is deposited by vacuum-assisted spin coating technique. Then a uniform TiN barrier layer is fabricated using atomic layer deposition (ALD) at 270 °C. The seed layer is fabricated by sequentially applying sputtering and electroless plating of Cu. Notably, with the pre-treatment effect of sputtered Cu, the electroless plating process is able to form a continuous Cu layer in high aspect ratio vias. Dense and continuous Cu seed layers are successfully fabricated in TSVs with diameters of 3 µm and 5 µm, respectively. The aspect ratios of the TSVs are larger than 17. The minimum thickness of the Cu seed layer inside TSVs is around 100 nm, and such a continuous seed layer is beneficial to the subsequent electroplating of Cu conductor. The proposed process flow for the formation of liner, barrier and seed layer in ultra-high aspect ratio TSVs is useful for the fabrication of interconnects in heterogeneous integration of various modern electronic systems and devices.\",\"PeriodicalId\":351817,\"journal\":{\"name\":\"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ECTC32696.2021.00300\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC32696.2021.00300","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Development of Cu Seed Layers in Ultra-High Aspect Ratio Through-Silicon-Vias (TSVs) with Small Diameters
Through-silicon-vias (TSVs) with high aspect ratio are of great demand due to their advantages in high density three-dimensional (3D) integration. This paper presents a feasible and convenient process flow for fabricating insulation layer, barrier and seed layer in ultra-high aspect ratio TSVs. A conformal polyimide (PI) liner is deposited by vacuum-assisted spin coating technique. Then a uniform TiN barrier layer is fabricated using atomic layer deposition (ALD) at 270 °C. The seed layer is fabricated by sequentially applying sputtering and electroless plating of Cu. Notably, with the pre-treatment effect of sputtered Cu, the electroless plating process is able to form a continuous Cu layer in high aspect ratio vias. Dense and continuous Cu seed layers are successfully fabricated in TSVs with diameters of 3 µm and 5 µm, respectively. The aspect ratios of the TSVs are larger than 17. The minimum thickness of the Cu seed layer inside TSVs is around 100 nm, and such a continuous seed layer is beneficial to the subsequent electroplating of Cu conductor. The proposed process flow for the formation of liner, barrier and seed layer in ultra-high aspect ratio TSVs is useful for the fabrication of interconnects in heterogeneous integration of various modern electronic systems and devices.