Corrosion/migration study of flip chip underfill and ceramic overcoating

Temperature, humidity and voltage (bias) represent a well-known combination of stress parameters that activate failure mechanisms and decrease reliability of microelectronic packages. The following work focuses mainly on the impact of such mechanisms on a high volume flip chip package at IBM. This package consists of a silicon flip chip on alumina with C4 enhancement underfill and a package overcoat The test conditions for HAST were 130 C, 85%RH and 5 V, while 85 C, 85% RH and 5 V were used for THB. In order to have a sampling most representative of manufacturing conditions, two IBM manufacturing sites were selected to both build and stress parts. Parts were selected from respective sites at a rate of 6 parts per week over a 6-month period. Results showed that the underfill and overcoating environment postpones the metal migration mechanism far beyond the product life cycle. The study also revealed that the Cr/Cu/Cr conductor lines and the Pb/Sn C4 structures were the regions most susceptible to migration. The acceleration factor of copper conductor migration between HAST and THB was 86 based on a visual inspection at 100X, yielding an activation energy (Ea) of 1.23 eV using the Arrhenius model. It was not possible to calculate the acceleration factor involving Pb/Sn sites, but electrical failures were found in HAST. The failure mechanism was Pb migration between C4 balls and the nearest Cr/Cu/Cr conductor line. It has also been identified that a C4 having a large void will fail earlier due to the bigger diameter. Based on a recent study (S. Peck), the average Ea in the microelectronics packaging industry has evolved from 0.79 eV some 10 years ago to about 0.9 eV today. In light of this, an Ea of 1.23 ev (copper migration) for an application with 50 microns cathode-to-anode is deemed very acceptable.