用于高性能ASIC的低电压0.35 /spl mu/m CMOS/SOI技术

Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI:10.1109/CICC.1997.606659

A. Adan, T. Naka, S. Kaneko, D. Urabe, K. Higashi, A. Kagisawa

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引用次数: 0

摘要

介绍了在超薄SOI (Shallow SIMOX)晶圆上实现的用于低压高性能ASIC的0.35 /spl mu/m CMOS工艺。在1.5v的低电压下，稳定、高速、低v的晶体管被集成在一个盐化双栅极工艺中。浅SIMOX器件耗散了1/5的Bulk-Si功率。一个原型锁相环电路在1.5v电源电压下工作在1.6 GHz的fmax，证明了该技术的优异性能。

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Low-voltage 0.35 /spl mu/m CMOS/SOI technology for high-performance ASIC's

A 0.35 /spl mu/m CMOS process for low-voltage, high-performance ASIC's, implemented on ultra-thin SOI (Shallow SIMOX) wafers, is described. Stable high speed, low-Vth transistors for low-voltage operation at 1.5v are integrated in a salicided dual-gate process. Shallow SIMOX devices dissipate 1/5 of the Bulk-Si power. A prototype PLL circuit operates at fmax of 1.6 GHz at 1.5v supply voltage, demonstrating the excellent performance of this technology.

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Proceedings of CICC 97 - Custom Integrated Circuits Conference

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