类故障注入的VHDL描述:一种方法和初步结果

Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2001-10-24 DOI:10.1109/DFTVS.2001.966778

R. Velazco, R. Leveugle, O. Calvo

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引用次数: 19

摘要

研究了一种方法，使人们能够评估单个事件干扰现象对处理器可靠运行的影响。该方法基于使用高级电路描述的修改版本的位翻转仿真。初步结果说明了这种新策略的潜力。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Upset-like fault injection in VHDL descriptions: A method and preliminary results

Investigates an approach allowing one to evaluate the consequences of single event upset phenomena for the reliable operation of processors. The method is based on the simulation of bit flips using a modified version of a high-level circuit description. Preliminary results illustrate the potential of this new strategy.

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Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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