VLSI互连中电感耦合的解析串扰模型

J. Ravindra, M. Srinivas
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引用次数: 1

摘要

对于深亚微米(DSM)互连,由于时钟速度的增加,芯片上的感应效应正在上升,减少互连长度和信号上升时间是信号完整性和整体互连性能的主要关注点。电感会在信号波形中产生噪声,对电路的性能和信号的完整性产生不利影响。对于全局导线,由于这些线路的电阻较低,使得导线阻抗的无功分量与电阻分量相当,并且由于较长的电流返回路径导致导线之间存在显着的互感耦合,因此电感效应更为严重。本文提出了DSM技术中电感串扰的分析模型。仿真结果表明,电感耦合对长互连的影响是显著的,而对局部互连的影响几乎不显著,侵入器的自感对串扰噪声的影响更大。所有仿真结果均使用Cadence公司的动态电路模拟器SPECTRE进行。
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Analytical crosstalk model with inductive coupling in VLSI interconnects
For deep submicron (DSM) interconnects on-chip inductive effects are rising due to increasing clock speeds, decreasing interconnect lengths and signal rise times are the major concern for signal integrity and overall interconnect performance. Inductance causes noise in the signal waveforms, which can adversely affect the performance of the circuit and signal integrity. For global wires inductance effects are more severe due to the lower resistance of these lines, which makes the reactive component of the wire impedance comparable to the resistive component, and also due to the presence of significant mutual inductive coupling between wires resulting from longer current return paths. This paper addresses an analytical model for inductive crosstalk for DSM technologies. Simulation results show that the effect of inductive coupling for long interconnects is significant but it is almost insignificant for local interconnects and the self inductance of the aggressor has more impact on crosstalk noise. All the simulations results carried out using Cadence's dynamic circuit simulator SPECTRE.
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