A novel power reduction technique using wire multiplexing

Power consumption reduction is a very critical challenge in nowadays nanoscale circuits. In this paper, a new power reduction approach is demonstrated. This approach is originally based on the idea of TSV multiplexing in 3D-ICs where two or more signals can flow through one TSV instead of multiple TSVs. Based on that behavior, the possibility of power reduction of this circuit is discovered and its generalization to any wire, i.e., wire multiplexing, is detailed. Also, an analytical power model for this circuit is developed to predict its power consumption behavior. Further, and by means of Cadence-Spectre simulations on 65 nm technology and also using the developed analytical model, the power reduction of wire multiplexing technique could be proved and verified.