Omar R. Avila-Lopez, R. Parra-Michel, F. Sandoval-Ibarra, M. Aguirre-Hernandez
{"title":"在0.5µm CMOS工艺中设计和实现900MHz无源标签的基带部分","authors":"Omar R. Avila-Lopez, R. Parra-Michel, F. Sandoval-Ibarra, M. Aguirre-Hernandez","doi":"10.1109/MWSCAS.2009.5236100","DOIUrl":null,"url":null,"abstract":"The design and implementation of digital circuitry for building a 900MHz passive tag in a standard 0.5µm CMOS technology is presented. The digital circuitry (hereafter called Digital Section, DS) including a voltage-controlled oscillator (VCO) satisfies the baseband requirements of ISO/IEC18000-6 type A standard. To verify the DS's functionality, a basic Tag-Reader was designed in order to apply test sequences. Power consumption, maximum operation frequency, and area utilization analyses were done using Synopsys' Design Compiler. The obtained results show that the proposed architecture fulfils the requirements stated for the implementation.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design and implementation of the baseband section for a 900MHz passive tag in a 0.5µm CMOS process\",\"authors\":\"Omar R. Avila-Lopez, R. Parra-Michel, F. Sandoval-Ibarra, M. Aguirre-Hernandez\",\"doi\":\"10.1109/MWSCAS.2009.5236100\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The design and implementation of digital circuitry for building a 900MHz passive tag in a standard 0.5µm CMOS technology is presented. The digital circuitry (hereafter called Digital Section, DS) including a voltage-controlled oscillator (VCO) satisfies the baseband requirements of ISO/IEC18000-6 type A standard. To verify the DS's functionality, a basic Tag-Reader was designed in order to apply test sequences. Power consumption, maximum operation frequency, and area utilization analyses were done using Synopsys' Design Compiler. The obtained results show that the proposed architecture fulfils the requirements stated for the implementation.\",\"PeriodicalId\":254577,\"journal\":{\"name\":\"2009 52nd IEEE International Midwest Symposium on Circuits and Systems\",\"volume\":\"29 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-09-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 52nd IEEE International Midwest Symposium on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS.2009.5236100\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2009.5236100","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design and implementation of the baseband section for a 900MHz passive tag in a 0.5µm CMOS process
The design and implementation of digital circuitry for building a 900MHz passive tag in a standard 0.5µm CMOS technology is presented. The digital circuitry (hereafter called Digital Section, DS) including a voltage-controlled oscillator (VCO) satisfies the baseband requirements of ISO/IEC18000-6 type A standard. To verify the DS's functionality, a basic Tag-Reader was designed in order to apply test sequences. Power consumption, maximum operation frequency, and area utilization analyses were done using Synopsys' Design Compiler. The obtained results show that the proposed architecture fulfils the requirements stated for the implementation.