A novel performance model for state-of-the-art processors by modernization of Rent's rule

Faithful a priori estimation of system performance has long been the foundation for early device, circuit, and micro-architectural evaluation. For over two decades, Rent's power-law has been a popular modelling methodology for predicting interconnect characteristics of a system. However, with dimensional scaling, interconnects have become increasingly important, and the existing models do not provide accurate interconnect estimates; at worst, current Rent's-based models heavily under-estimate interconnect delay and power. At the same time, microprocessor designs are also evolving to cope with the rapidly changing technology landscape, which together can drastically influence the overall performance characteristics of the designs. For the first time, this paper argues the validity of Rent's method in the era of rapid technology and microprocessor-design advancements. A new approach to Rent's model is proposed which addresses the inability of the current Rent's approach to accurately capture the standard cell level characteristics and microprocessor characteristics that are inherent to the way we design microprocessors today. The proposed models are validated against a rich database of state-of-the-art commercial microprocessors at 14/16nm, 10nm and 7nm process nodes, and the results illustrate the importance of design-specific technology prediction.