C. Tsai, Yun-Hsiang Wang, M. Kwan, P.-C. Chen, F. Yao, S.-C. Liu, J.-L. Yu, C. Yeh, R. Su, W. Wang, W. Yang, K.Y. Wong, Y.-S. Lin, M. Lin, H.-Y Wu, C.-M. Chen, C. Yu, C.-B. Wu, M. Chang, J.-S. You, T.M. Huang, S.P. Wang, L. Tsai, Chan-Hong Chern, H. Tuan, A. Kalnitsky
{"title":"智能GaN平台:性能与挑战","authors":"C. Tsai, Yun-Hsiang Wang, M. Kwan, P.-C. Chen, F. Yao, S.-C. Liu, J.-L. Yu, C. Yeh, R. Su, W. Wang, W. Yang, K.Y. Wong, Y.-S. Lin, M. Lin, H.-Y Wu, C.-M. Chen, C. Yu, C.-B. Wu, M. Chang, J.-S. You, T.M. Huang, S.P. Wang, L. Tsai, Chan-Hong Chern, H. Tuan, A. Kalnitsky","doi":"10.1109/IEDM.2017.8268488","DOIUrl":null,"url":null,"abstract":"This paper explores the next stage of GaN power devices with 2-level integration of peripheral low voltage active and passive devices. The 1st level consists of protection/control/driving circuits, which potentially improves the performance and overcomes the challenges to the power devices. The 2nd level integration has high-low side on-chip integration on a 100V technology platform. The challenge of channel modulation due to substrate bias sharing is effectively eliminated by the invented new scheme. The system efficiency of DC-DC buck converter using such scheme is enhanced with lower on-state resistance and good stability.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"49","resultStr":"{\"title\":\"Smart GaN platform: Performance & challenges\",\"authors\":\"C. Tsai, Yun-Hsiang Wang, M. Kwan, P.-C. Chen, F. Yao, S.-C. Liu, J.-L. Yu, C. Yeh, R. Su, W. Wang, W. Yang, K.Y. Wong, Y.-S. Lin, M. Lin, H.-Y Wu, C.-M. Chen, C. Yu, C.-B. Wu, M. Chang, J.-S. You, T.M. Huang, S.P. Wang, L. Tsai, Chan-Hong Chern, H. Tuan, A. Kalnitsky\",\"doi\":\"10.1109/IEDM.2017.8268488\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper explores the next stage of GaN power devices with 2-level integration of peripheral low voltage active and passive devices. The 1st level consists of protection/control/driving circuits, which potentially improves the performance and overcomes the challenges to the power devices. The 2nd level integration has high-low side on-chip integration on a 100V technology platform. The challenge of channel modulation due to substrate bias sharing is effectively eliminated by the invented new scheme. The system efficiency of DC-DC buck converter using such scheme is enhanced with lower on-state resistance and good stability.\",\"PeriodicalId\":412333,\"journal\":{\"name\":\"2017 IEEE International Electron Devices Meeting (IEDM)\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"49\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE International Electron Devices Meeting (IEDM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2017.8268488\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE International Electron Devices Meeting (IEDM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2017.8268488","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper explores the next stage of GaN power devices with 2-level integration of peripheral low voltage active and passive devices. The 1st level consists of protection/control/driving circuits, which potentially improves the performance and overcomes the challenges to the power devices. The 2nd level integration has high-low side on-chip integration on a 100V technology platform. The challenge of channel modulation due to substrate bias sharing is effectively eliminated by the invented new scheme. The system efficiency of DC-DC buck converter using such scheme is enhanced with lower on-state resistance and good stability.
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