H. Fukutome, K. Suh, W. Kim, Y. Moriyama, S. Kang, B. Eom, J. Kim, C. Yoon, W. Kwon, Y. Chung, Y. Nam, Y. Kim, S. Park, J. Park, H. Cho, K. Rim, S. Kwon
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Comprehensive Feasibility Study of Single FIN Transistors for Scaling Both Switching Energy and Device Footprint
We have comprehensively studied feasibility of single-fin (1-fin) devices from viewpoint of scaling switching energy (CV2) and device footprint width, which affects standard cell height. We have clarified methodology to lower minimum operation voltage (Vmin) of flip-flop (F/F) featuring 1-fin devices in order to maximize gain of CV2. For the first time, we have demonstrated Vmin of 1-fin F/F same as 2-fin one and 27% CV2 reduction with keeping speed at a constant leakage.