VHDL modelling and simulation of parallel-beam filtered backprojection for CT image reconstruction

This paper describes the VHDL modelling and simulation of parallel-beam filtered backprojection algorithm to be used for image reconstruction in CT (computed tomography). The algorithm being highly data intensive and computationally extensive requires a lot of time for execution and hence it necessitates hardware implementation for real-time processing. So the VHDL model can be implemented on reconfigurable hardware. Due to memory constraints a smaller size image has been implemented on FPGA while the VHDL model has been designed for a 512×512 image which can be implemented on FPGA using offchip memory blocks.