垂直通道晶体管(VCT)作为未来4F2 DRAM架构的接入晶体管

Daohuan Feng, Yi Jiang, Yunsong Qiu, Yuhong Zheng, Harry Kim, Jaewoo Kim, Jian Chu, Guangsu Shao, Yucheng Liao, Cheng-Jer Yang, Minrui Hu, Wenli Zhao, Linjiang Xia, Jianfeng Xiao, Di Ma, Yuan Cheng, Xiangbo Kong, Chao Lin, Tianming Li, Yongjie Li, Jingheng Meng, K. Shao, Yan Wang, Xiaoan Yang, Xiang Liu, Qinghua Han, Huiming Li, Yanzhe Tang, Mingde Liu, Eric Wu, Xiaopeng Li, Renrui Huang, Mingtang Zhang, Long Hou, Xuan Pan, Xinwen Jin, Shuiping Zhao, D. Han, Ted C. Park, Deyuan Xiao, Chao Zhao, A. Yoo
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引用次数: 0

摘要

在这项工作中,提出了一种针对下一代DRAM的新型4F2 VCT(垂直沟道晶体管)。通过TCAD仿真分析了$\mathbf{4 F}^{2}$ VCT的工艺可行性和器件性能。详细的过程,如BL(位线)和WL(字线)循环也讨论了实现lx节点VCT DRAM。首次成功实现了密度高达$198\ \ mathm {Mbit}/\ mathm {mm}^{2}$的$8\ mathm {~Gb}$全阵列VCT的硅演示。此外,我们还演示了具有合理器件性能的VCT接入晶体管的标准开关行为。
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Vertical Channel Transistor (VCT) as Access Transistor for Future 4F2 DRAM Architecture
In this work, a novel 4F2 VCT (vertical channel transistor) targeting for next generation of DRAM is proposed. We approached process feasibility and device performance of $\mathbf{4 F}^{2}$ VCT by TCAD simulation. Detailed processes such as BL (bit line) and WL (word line) loop have also been discussed to achieve lx node VCT DRAM. For the first time, silicon demonstration for $8\mathrm{~Gb}$ full array VCT with density as high as $198\ \mathrm{Mbit}/\mathrm{mm}^{2}$ is successfully realized. Besides, we also demonstrated standard switching behavior of VCT access transistor with reasonable device performance.
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