{"title":"采用180nm CMOS技术的单片2.4GHz正交LNA-IQ混频器","authors":"Zechariah Balan, H. Ramiah, J. Rajendran","doi":"10.1109/PRIMEASIA.2017.8280365","DOIUrl":null,"url":null,"abstract":"This paper presents a 2.4GHz single chip quadrature low noise amplifier (QLNA) and IQ mixer in standard 180 nm CMOS technology. Quadrature generation is achieved in the RF path using a type-II RC-CR network which exhibits good phase and amplitude balance while reducing insertion loss making it less vulnerable to process variations and external components. Various circuit techniques such as PCSNIM and low power optimization are adopted to acquire good performance with respect to power consumption and cost. In the implementation of LNA stage, an inductive source degeneration and inductive loading is used for low noise, high gain and good input matching. The mixing stage integrates an active IQ mixer with low pass filter (LPF) load. Current bleeding technique is adopted to further improve the conversion gain and noise performance. The extracted results of this proposed design shows a high gain of 22dB at IF frequency of 100MHz with a noise figure (NF) of 9dB. The input 1-dB compression point (P1DB) and input referred third-order intercept point (IIP3) are −20 dBm and −11dBm respectively. The overall QLNA-mixer consumes 3.5 mA of current from a 1.8 V headroom.","PeriodicalId":335218,"journal":{"name":"2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A single chip 2.4GHz quadrature LNA-IQ mixer in 180nm CMOS technology\",\"authors\":\"Zechariah Balan, H. Ramiah, J. Rajendran\",\"doi\":\"10.1109/PRIMEASIA.2017.8280365\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a 2.4GHz single chip quadrature low noise amplifier (QLNA) and IQ mixer in standard 180 nm CMOS technology. Quadrature generation is achieved in the RF path using a type-II RC-CR network which exhibits good phase and amplitude balance while reducing insertion loss making it less vulnerable to process variations and external components. Various circuit techniques such as PCSNIM and low power optimization are adopted to acquire good performance with respect to power consumption and cost. In the implementation of LNA stage, an inductive source degeneration and inductive loading is used for low noise, high gain and good input matching. The mixing stage integrates an active IQ mixer with low pass filter (LPF) load. Current bleeding technique is adopted to further improve the conversion gain and noise performance. The extracted results of this proposed design shows a high gain of 22dB at IF frequency of 100MHz with a noise figure (NF) of 9dB. The input 1-dB compression point (P1DB) and input referred third-order intercept point (IIP3) are −20 dBm and −11dBm respectively. The overall QLNA-mixer consumes 3.5 mA of current from a 1.8 V headroom.\",\"PeriodicalId\":335218,\"journal\":{\"name\":\"2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/PRIMEASIA.2017.8280365\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PRIMEASIA.2017.8280365","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A single chip 2.4GHz quadrature LNA-IQ mixer in 180nm CMOS technology
This paper presents a 2.4GHz single chip quadrature low noise amplifier (QLNA) and IQ mixer in standard 180 nm CMOS technology. Quadrature generation is achieved in the RF path using a type-II RC-CR network which exhibits good phase and amplitude balance while reducing insertion loss making it less vulnerable to process variations and external components. Various circuit techniques such as PCSNIM and low power optimization are adopted to acquire good performance with respect to power consumption and cost. In the implementation of LNA stage, an inductive source degeneration and inductive loading is used for low noise, high gain and good input matching. The mixing stage integrates an active IQ mixer with low pass filter (LPF) load. Current bleeding technique is adopted to further improve the conversion gain and noise performance. The extracted results of this proposed design shows a high gain of 22dB at IF frequency of 100MHz with a noise figure (NF) of 9dB. The input 1-dB compression point (P1DB) and input referred third-order intercept point (IIP3) are −20 dBm and −11dBm respectively. The overall QLNA-mixer consumes 3.5 mA of current from a 1.8 V headroom.