{"title":"具有无损数据压缩功能的590MDE/s半全局匹配处理器","authors":"Kyeongryeol Bong, K. Lee, H. Yoo","doi":"10.1109/SOCC.2017.8225998","DOIUrl":null,"url":null,"abstract":"A tile-based semi-global matching (SGM) processor with lossless data compression is proposed. The 8×8 tile-base processing and the P2-less data compression can reduce the external memory access by 85% without any change in the processing result. In addition, the P2-less data compression can decrease on-chip SRAM size by 50%. Implemented in 65nm CMOS technology, the 6.3mm2 chip consumes 288mW and supports 590MDE/s (million disparity estimation per second) when processing 640×360 resolution with 64-disparity range at 40fps real-time operation.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 590MDE/s semi-global matching processor with lossless data compression\",\"authors\":\"Kyeongryeol Bong, K. Lee, H. Yoo\",\"doi\":\"10.1109/SOCC.2017.8225998\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A tile-based semi-global matching (SGM) processor with lossless data compression is proposed. The 8×8 tile-base processing and the P2-less data compression can reduce the external memory access by 85% without any change in the processing result. In addition, the P2-less data compression can decrease on-chip SRAM size by 50%. Implemented in 65nm CMOS technology, the 6.3mm2 chip consumes 288mW and supports 590MDE/s (million disparity estimation per second) when processing 640×360 resolution with 64-disparity range at 40fps real-time operation.\",\"PeriodicalId\":366264,\"journal\":{\"name\":\"2017 30th IEEE International System-on-Chip Conference (SOCC)\",\"volume\":\"29 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 30th IEEE International System-on-Chip Conference (SOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCC.2017.8225998\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 30th IEEE International System-on-Chip Conference (SOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCC.2017.8225998","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 590MDE/s semi-global matching processor with lossless data compression
A tile-based semi-global matching (SGM) processor with lossless data compression is proposed. The 8×8 tile-base processing and the P2-less data compression can reduce the external memory access by 85% without any change in the processing result. In addition, the P2-less data compression can decrease on-chip SRAM size by 50%. Implemented in 65nm CMOS technology, the 6.3mm2 chip consumes 288mW and supports 590MDE/s (million disparity estimation per second) when processing 640×360 resolution with 64-disparity range at 40fps real-time operation.
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