设计了一种检测宽量程仪表放大器混合信号干扰的测试芯片

Neeraj Agarwal, Neeru Agarwal, Manisha Sharma
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引用次数: 0

摘要

本文描述并论证了片上系统设计中与衬底耦合有关的问题,包括产生衬底耦合的物理现象、耦合传输机制和介质、影响耦合强度的参数及其对混合信号集成电路的影响。在0.8pm N井P子CMOS技术5V双聚双金属工艺中,设计了一种检测混合信号各方面干扰的测试芯片。芯片的基本目的是找出模拟电路和数字电路相邻放置在同一基片上时所产生的干扰大小。设计了一种具有高CMRR的仪表放大器,用于噪声检测。仪表放大器输入端的MOSFET电容用于基片干扰的拾取。
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Design a test chip to find out mixed signal interference with broad range instrumentation amplifier
In this Paper, issues related to substrate coupling in system on chip design are described and demonstrated including the physical phenomenon responsible for its creation, coupling transmission mechanism and media, parameter affecting coupling strengths and its impact on mixed signal integrated circuits. A test chip to find out various aspect of mixed signal interference is planned in 0.8pm N well P sub CMOS technology 5V double poly double metal process. Basic aim of chip is to find out magnitude of interference happening when analog and digital circuit is placed nearby on a common substrate. An instrumentation amplifier with high CMRR is also designed for noise sensing. MOSFET capacitors at the input of instrumentation amplifier are used for the picking of substrate interference.
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