基于低分辨率量化的MPEG2视频编码新运动估计

Seongsoo Lee, Jeong-Min Kim, S. Chae
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引用次数: 2

摘要

提出了一种用于MPEG2视频编码的实时运动估计算法。采用了低比特分辨率量化和新的匹配准则,降低了计算量。为了保持性能,我们先进行低分辨率搜索,然后再进行全分辨率搜索。仿真结果表明,在CCIR601图像的-32.0/spl sim/+31.5搜索范围内,与全搜索算法相比,该算法的计算成本为1/17.4,性能下降小于0.37 dB。并给出了基于该算法的实时MPEG2运动估计器的结构。它同时搜索-32.0/spl sim/+31.5搜索范围的两种预测模式。其硬件复杂性估计约为100,000个随机逻辑门和90 kb的SRAM。采用0.5 /spl mu/m三金属CMOS标准电池技术的拟议架构的VLSI设计正在进行中。
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New motion estimation using low-resolution quantization for MPEG2 video encoding
We propose a new algorithm of real-time motion estimation for MPEG2 video encoding. It reduces the computational cost by using low bit-resolution quantization and new matching criterion. To maintain the performance, we employed a low-resolution search followed by a full-resolution search. Simulation results show that the proposed algorithm requires 1/17.4 computational cost while maintaining the performance degradation less than 0.37 dB with respect to the full search algorithm for -32.0/spl sim/+31.5 search range in the CCIR601 image. The architecture for the real-time MPEG2 motion estimator using this algorithm is also explained. It searches concurrently two prediction modes for -32.0/spl sim/+31.5 search range. Its hardware complexity is estimated to about 100,000 gates of random logic and 90 Kbits of SRAM. A VLSI design of the proposed architecture is in progress using a 0.5 /spl mu/m triple-metal CMOS standard-cell technology.
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Real-time MPEG-2 software decoding with a dual-issue RISC processor A chip set for a ray-casting engine An object based data cache with conflict free concurrent access as shared memory for a parallel DSP A 500 MHz, one volt, 16 by 16 bit multiplier for DSP cores A parallel architecture for rapid prototyping of mechatronic algorithms by exploiting implicit fine-grain parallelism
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