{"title":"基于直方图测试技术的ADC BIST方案","authors":"F. Azaïs, S. Bernard, Y. Betrand, M. Renovell","doi":"10.1109/ETW.2000.873779","DOIUrl":null,"url":null,"abstract":"This paper discusses the viability of a BIST implementation for the sinusoidal histogram technique classically used for ADC testing. An original approach based on (i) approximations to estimate the ADC parameters, (ii) decomposition of the global test in a code-after-code test procedure and (iii) piecewise approximation to compute the ideal histogram is developed. These three features allow a significant reduction of the required operative resources as well as the required memory resources dedicated to the storage of both experimental and reference data.","PeriodicalId":255826,"journal":{"name":"Proceedings IEEE European Test Workshop","volume":"72 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"85","resultStr":"{\"title\":\"Towards an ADC BIST scheme using the histogram test technique\",\"authors\":\"F. Azaïs, S. Bernard, Y. Betrand, M. Renovell\",\"doi\":\"10.1109/ETW.2000.873779\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper discusses the viability of a BIST implementation for the sinusoidal histogram technique classically used for ADC testing. An original approach based on (i) approximations to estimate the ADC parameters, (ii) decomposition of the global test in a code-after-code test procedure and (iii) piecewise approximation to compute the ideal histogram is developed. These three features allow a significant reduction of the required operative resources as well as the required memory resources dedicated to the storage of both experimental and reference data.\",\"PeriodicalId\":255826,\"journal\":{\"name\":\"Proceedings IEEE European Test Workshop\",\"volume\":\"72 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-05-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"85\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings IEEE European Test Workshop\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ETW.2000.873779\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings IEEE European Test Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ETW.2000.873779","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Towards an ADC BIST scheme using the histogram test technique
This paper discusses the viability of a BIST implementation for the sinusoidal histogram technique classically used for ADC testing. An original approach based on (i) approximations to estimate the ADC parameters, (ii) decomposition of the global test in a code-after-code test procedure and (iii) piecewise approximation to compute the ideal histogram is developed. These three features allow a significant reduction of the required operative resources as well as the required memory resources dedicated to the storage of both experimental and reference data.
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