Designing bio-inspired autonomous error-tolerant massively parallel computing architectures

The scalable and massively parallel computing systems composed of many processors, which are connected on chips that will become more and more complex and unreliable. This paper presents a bio-inspired error tolerance framework and three design principles based on the Autonomous Error Tolerant (AET) architecture. A nearby error perception mechanism is carefully designed to detect faults and an initiative evolutions strategy is studied to handle unrecoverable errors. A circuit backup mechanism is proposed for generating an effective way by setting the routing rules to bypass the failed link or node to achieve fault tolerance capabilities. The print circuit board (PCB) prototype is designed and implemented based on a reconfigurable and scalable control-centric dual-core embedded processor (ReSC). Different testing programs associating fault-detection or self-backup schemes and routing algorithms are explored in the platform. Experimental results show that error perceptron can detect the faults and reassign the task for other remaining free and healthy AET cell through Network-on-chip (NoC) when faults occur at the AET cell. The system can complete error recovery within 3 seconds, the paper shows the error-tolerant capability of the proposed architecture is better than the conventional multi-modular redundant system.